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rev.5.00, nov. 17.2003, page 1 of 23 hn58c256a series hn58c257a series 256k eeprom (32-kword 8-bit) ready/ busy and res function (hn58c257a) rej03c0148-0500z (previous ade-203-410d (z) rev. 4.0) rev. 5.00 nov. 17. 2003 description renesas technology 's hn58c256a and hn58c257a are electrically erasable and programmable roms organized as 32768-word 8-bit. they have realized high speed low power consumption and high reliability by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features ? single 5 v supply: 5 v 10% ? access time: 85 ns/100 ns (max) ? power dissipation ? active: 20 mw/mhz, (typ) ? standby: 110 w (max) ? on-chip latches: address, data, ce , oe , we ? automatic byte write: 10 ms max ? automatic page write (64 bytes): 10 ms max ? ready/ busy (only the hn58c257a series) ? data polling and toggle bit ? data protection circuit on power on/off ? conforms to jedec byte-wide standard ? reliable cmos with mnos cell technology ? 10 5 erase/write cycles (in page mode) ? 10 years data retention ? software data protection ? write protection by res pin (only the hn58c257a series) ? industrial versions (temperatur range: ? 20 to 85 c and ? 40 to 85 c) are also available. ? there are also lead free products.
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 2 of 23 ordering information type no. access time package hn58c256ap-85 hn58c256ap-10 85 ns 100 ns 600 mil 28-pin plastic dip (dp-28) hn58c256afp-85 hn58c256afp-10 85 ns 100 ns 400 mil 28-pin plastic sop (fp-28d) HN58C256AT-85 hn58c256at-10 85 ns 100 ns 28-pin plastic tsop (tfp-28db) hn58c257at-85 hn58c257at-10 85 ns 100 ns 32-pin plastic tsop (tfp-32da) hn58c256afp-85e hn58c256afp-10e 85 ns 100 ns 400 mil 28-pin plastic sop (fp-28dv) lead free HN58C256AT-85e hn58c256at-10e 85 ns 100 ns 28-pin plastic tsop (tfp-28dbv) lead free hn58c257at-85e hn58c257at-10e 85 ns 100 ns 32-pin plastic tsop (tfp-32dav) lead free pin arrangement hn58c256ap/afp series hn58c256at series hn58c257at series (top view) (top view) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 17 18 19 20 21 22 23 24 25 26 27 28 29 30 16 15 14 13 12 11 10 9 8 7 6 5 4 3 31 32 2 1 nc nc res rdy/ busy
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 3 of 23 pin description pin name function a0 to a14 address input i/o0 to i/o7 data input/output oe output enable ce chip enable we write enable v cc power supply v ss ground rdy/ busy * 1 ready busy res * 1 reset nc no connection note: 1. this function is supported by only the hn58c257a series. block diagram note: 1. this function is supported by only the hn58c257a series. v v oe ce a5 a0 a6 a14 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch res rdy/ busy res * 1 * 1 * 1 to to to
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 4 of 23 operation table operation ce ce ce ce oe oe oe oe we we we we res res res res * 3 rdy/ busy busy busy busy * 3 i/o read v il v il v ih v h * 1 high-z dout standby v ih * 2 high-z high-z write v il v ih v il v h high-z to v ol din deselect v il v ih v ih v h high-z high-z write inhibit v ih ? ? v il ? ? data polling v il v il v ih v h v ol dout (i/o7) program reset v il high-z high-z notes: 1. refer to the recommended dc operating condition. 2. : don?t care 3. this function is supported by only the hn58c257a series. absolute maximum ratings parameter symbol value unit power supply voltage rerative to v ss v cc ? 0.6 to +7.0 v input voltage rerative to v ss vin ? 0.5 * 1 to +7.0 * 3 v operationg temperature range * 2 topr 0 to +70 c storage temperature range tstg ? 55 to +125 c notes: 1. vin min = ? 3.0 v for pulse width 50 ns 2. including electrical characteristics and data retention 3. should not exceed v cc + 1 v. recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 0 0 0 v input voltage v il ? 0.3 * 1 ? 0.8 v v ih 2.2 ? v cc + 0.3 * 2 v v h * 3 v cc ? 0.5 ? v cc + 1.0 v operating temperature topr 0 ? +70 c notes: 1. v il min: ?1.0 v for pulse width 50 ns. 2. v ih max: v cc + 1.0 v for pulse width 50 ns. 3. this function is supported by only the hn58c257a series.
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 5 of 23 dc characteristics (ta = 0 to +70 c, v cc = 5.0 v 10 % ) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2 * 1 a v cc = 5.5 v, vin = 5.5 v output leakage current i lo ? ? 2 a v cc = 5.5 v, vout = 5.5/0.4 v standby v cc current i cc1 ? ? 20 a ce = v cc i cc2 ? ? 1 ma ce = v ih operating v cc current i cc3 ? ? 12 ma iout = 0 ma, duty = 100 % , cycle = 1 s, v cc = 5.5 v ? ? 30 ma iout = 0 ma, duty = 100 % , cycle = 85 ns, v cc = 5.5 v output low voltage v ol ? ? 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 ? ? v i oh = ? 400 a note: 1. i li on res = 100 a max (only the hn58c257a series) capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance * 1 cin ? ? 6 pf vin = 0 v output capacitance * 1 cout ? ? 12 pf vout = 0 v note: 1. this parameter is periodically sampled and not 100 % tested.
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 6 of 23 ac characteristics (ta = 0 to +70 c, v cc = 5 v 10 % ) test conditions ? input pulse levels: 0.4 v to 3.0 v, 0 v to v cc ( res pin* 2 ) ? input rise and fall time: 5 ns ? input timing reference levels: 0.8, 2.0 v ? output load: 1ttl gate +100 pf ? output reference levels: 1.5 v, 1.5 v read cycle hn58c256a/hn58c257a -85 -10 parameter symbol min max min max unit test conditions address to output delay t acc ? 85 ? 100 ns ce = oe = v il , we = v ih ce to output delay t ce ? 85 ? 100 ns oe = v il , we = v ih oe to output delay t oe 10 40 10 50 ns ce = v il , we = v ih address to output hold t oh 0 ? 0 ? ns ce = oe = v il , we = v ih oe ( ce ) high to output float * 1 t df 0 40 0 40 ns ce = v il , we = v ih res low to output float * 1, 2 t dfr 0 350 0 350 ns ce = oe = v il , we = v ih res to output delay * 2 t rr 0 450 0 450 ns ce = oe = v il , we = v ih
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 7 of 23 write cycle parameter symbol min * 3 typ max unit test conditions address setup time t as 0 ? ? ns address hold time t ah 50 ? ? ns ce to write setup time ( we controlled) t cs 0 ? ? ns ce hold time ( we controlled) t ch 0 ? ? ns we to write setup time ( ce controlled) t ws 0 ? ? ns we hold time ( ce controlled) t wh 0 ? ? ns oe to write setup time t oes 0 ? ? ns oe hold time t oeh 0 ? ? ns data setup time t ds 50 ? ? ns data hold time t dh 0 ? ? ns we pulse width ( we controlled) t wp 100 ? ? ns ce pulse width ( ce controlled) t cw 100 ? ? ns data latch time t dl 50 ? ? ns byte load cycle t blc 0.2 ? 30 s byte load window t bl 100 ? ? s write cycle time t wc ? ? 10 * 4 ms time to device busy t db 120 ? ? ns write start time t dw 0 * 5 ? ? ns reset protect time * 2 t rp 100 ? ? s reset high time * 2, 6 t res 1 ? ? s notes: 1. t df and t dfr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. this function is supported by only the hn58c257a series. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy (only the hn58c257a series) are used. this device automatically completes the internal write operation within this value. 5. next read or write operation can be initiated after t dw if polling techniques or rdy/ busy (only the hn58c257a series) are used. 6. this parameter is sampled and not 100 % tested. 7. a6 through a14 are page address and these addresses are latched at the first falling edge of we . 8. a6 through a14 are page address and these addresses are latched at the first falling edge of ce . 9. see ac read characteristics.
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 8 of 23 timing waveforms read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df t rr t dfr res * 2
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 9 of 23 byte write timing waveform (1) ( we controlled) address ce we oe din rdy/ busy * 2 t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db t rp res * 2 v cc t res high-z high-z t dw
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 10 of 23 byte write timing waveform (2) ( ce controlled) address ce we oe din rdy/ busy * 2 t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t rp res * 2 v cc t cw t bl t dw t res high-z high-z
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 11 of 23 page write timing waveform (1) ( we controlled) address a0 to a14 we ce oe din rdy/ busy * 2 t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t ch t cs t wp t dl t blc t ds t dw high-z high-z *7
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 12 of 23 page write timing waveform (2) ( ce controlled) address a0 to a14 we ce oe din rdy/ busy * 2 t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t wh t ws t cw t dl t blc t ds t dw high-z high-z *8
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 13 of 23 data data data data polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x *9 *9 an
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 14 of 23 toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from ?1? to ?0? (toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is "1". 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 address *3 *3 *4 din
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 15 of 23 software data protection timing waveform (1) (in protection mode) v ce we address data 5555 aa 2aaa 55 5555 a0 t blc t wc cc write address write data software data protection timing waveform (2) (in non-protection mode) v ce we address data t wc cc normal active mode 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 20
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 16 of 23 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 s from the preceding falling edge of we or ce . when ce or we is high for 100 s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data data data data polling data polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ busy busy busy busy signal ( only the hn58c257a series ) rdy/ busy signal also allows status of the eeprom to be determined. the rdy/ busy signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ busy signal changes state to high impedance. res res res res signal ( only the hn58c257a series ) when res is low, the eeprom cannot be read or programmed. therefore, data can be protected by keeping res low when v cc is switched. res should be high during read and programming because it doesn't provide a latch function. v program inhibit cc res program inhibit read inhibit read inhibit we we we we , ce ce ce ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce .
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 17 of 23 write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page- programmed less than 10 4 cycles. data protection to prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less. 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. be careful not to allow noise of a width of more than 20 ns on the control pins. we ce oe v 0 v v 0 v 20 ns max ih ih
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 18 of 23 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom shoud be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * * 2.1 protection by ce , oe , we to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : don ? t care. v cc : pull-up to v cc level. v ss : pull-down to v ss level. 2.2 protection by res (only the hn58c257a series) the unprogrammable state can be realized by that the cpu?s reset signal inputs directly to the eeprom?s res pin. res should be kept v ss level during v cc on/off. the eeprom breaks off programming operation when res becomes low, programming operation doesn?t finish correctly in case that res falls low during programming operation. res should be kept high for 10 ms after the last data input. v cc res we or ce 100 ? min 10 ms min 1 ? min program inhibit program inhibit
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 19 of 23 3. software data protection to prevent unintentional programming, this device has the software data protection (sdp) mode. the sdp is enabled by inputting the following 3 bytes code and write data. sdp is not enabled if only the 3 bytes code is input. to program data in the sdp enable mode, 3 bytes code must be input before write data. data aa 55 a0 write data } address 5555 2aaa 5555 write address normal data input the sdp mode is disabled by inputting the following 6 bytes code. note that, if data is input in the sdp disable cycle, data can not be written. data aa 55 80 aa 55 20 address 5555 2aaa 5555 5555 2aaa 5555 the software data protection is not enabled at the shipment. note: there are some differences between renesas technology?s and other company?s for enable/disable sequence of software data protection. if there are any questions , please contact with renesas technology?s sales offices.
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 20 of 23 package dimensions hn58c256ap series (dp-28) package code jedec jeita mass (reference value) dp-28 ? conforms 4.6 g 0.51 min 2.54 min 0.25 + 0.11 ? 0.05 2.54 ?0.25 0.48 ?0.10 0 ? ?15 ? 15.24 1.2 35.6 36.5 max 13.4 14.6 max 1 14 15 28 5.70 max 1.9 max unit: mm
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 21 of 23 package dimensions (cont.) hn58c256afp series (fp-28d, fp-28dv) package code jedec jeita mass (reference value) fp-28d, fp-28dv conforms 0.7 g *dimension including the plating thickness base material dimension 0 ? 8 ? *0.17 0.05 1.0 0.2 0.20 0.10 2.50 max 8.4 18.3 18.8 max 1.12 max 28 15 1 14 11.8 0.3 1.7 0.20 0.15 m 1.27 *0.40 0.08 0.38 0.06 0.15 0.04 unit: mm
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 22 of 23 package dimensions (cont.) hn58c256at series (tfp-28db, tfp-28dbv) package code jedec jeita mass (reference value) tfp-28db, tfp-28dbv 0.23 g *dimension including the plating thickness base material dimension 0.10 m 0.55 8.00 *0.22 0.08 13.40 0.30 *0.17 0.05 0.13 1.20 max 11.80 0 ? 5 ? 28 1 14 15 8.20 max 0.10 +0.07 0.08 0.50 0.10 0.80 0.45 max 0.20 0.06 0.15 0.04 unit: mm
hn58c256a series, hn58c257a series rev.5.00, nov. 17.2003, page 23 of 23 package dimensions (cont.) hn58c257at series (tfp-32da, tfp-32dav) 0.10 0.08 m 0.50 8.00 *0.22 0.08 14.00 0.20 1.20 max 12.40 32 116 17 *0.17 0.05 0.13 0.05 0 ? 5 ? 8.20 max 0.45 max 0.50 0.10 0.80 0.20 0.06 0.125 0.04 package code jedec jeita mass (reference value) tfp-32da, tfp-32dav conforms conforms 0.26 g *dimension including the plating thickness base material dimension unit: mm
revision history hn58c256a/hn58c257a series data sheet contents of modification rev. date page description 0.0 jun. 19. 1995 ? initial issue 1.0 may. 17. 1996 ? 4 4 5 6 change of format absolute maximun ratings addition of note 4 recommended dc operating conditions v ih (min): 3.0 v to 2.2 v dc characteristics v oh (min): v cc 0.8 v to 2.4 v ac characteristics input pulse levels: 0 v to 3.0 v to 0.4 v to 3.0 v data polling timing waveform addition of note 1 toggle bit waveform addition of note 4 2.0 feb. 27. 1997 4 16 recommended dc operating conditions v il (max): 0.6 v to 0.8 v functional description data protection 3: addition of note 3.0 may. 20. 1997 16 functional description data protection 3: change of description 4.0 oct. 24. 1997 8 timing waveforms read timing waveform: correct error 5.00 nov. 17. 2003 ? 2 20-23 change format issued by renesas technology corp. ordering information addition of hn58c256afp-85e , hn58c256afp-10e , HN58C256AT-85e, hn58c256at-10e, hn58c257at-85e, hn58c257at-10e package dimensions fp-28d to fp-28d, fp-28dv tfp-28db to tfp-28db, tfp-28dbv tfp-32da to tfp-32da, tfp-32dav
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

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